Current high-power field effect transistors, such as gallium nitride (GaN)-based heterostructure field effect transistors (HFETs), feature record high powers and breakdown voltages. Although these features make HFETs extremely promising for various applications in power electronics, certain material and device characteristics significantly limit the performance characteristics of the HFETs.
For example, FIG. 1 shows an illustrative schematic structure of a GaN-based HFET according to the prior art. The GaN-based HFET is essentially a normally-on device. In particular, the device channel (two-dimensional electron gas (2DEG)) is conducting between the source and drain of the HFET in the absence of a voltage bias applied to the gate. Such a characteristic is an important limitation for many power electronics applications since a gate voltage source failure can result in extremely high currents flowing through the power transistors and other connected circuit elements and result in partial or total damage to some of the components of the circuit.
One approach to achieve a normally-off condition in a GaN-based HFET removes a portion of the area under the gate, e.g., via etching or the like. For example, FIG. 2 shows an illustrative schematic structure of a recessed gate GaN-based HFET according to the prior art. A circuit-based approach uses a combination of GaN-based HFETs with normally-off silicon (Si)-based devices forming cascode connections, or Baliga pairs. For example, FIG. 3 shows an illustrative comparison of an AlGaN/GaN-based HFET with a cascode circuit according to the prior art.
However, both of these approaches lead to significant performance degradation. In particular, the recessed gate HFET shown in FIG. 2 has higher leakage current, a lower breakdown voltage, and a lower reliability as compared to the HFET shown in FIG. 1. Furthermore, the circuit of FIG. 3 includes significant parasitic parameters and adds additional series resistance of the Si-based devices to the overall circuit.